1. Field of the Invention
The present invention relates to semiconductor devices for which radiation resistance or punch through resistance is required and, more particularly, to N channel MOS transistors for which radiation resistance is required, or P channel MOS transistors for which punch through resistance is required.
2. Description of the Background Art
FIG. 22 is a graph illustrating the impurity concentration profile of a channel region underlying a gate electrode in a conventional MOS transistor. In the MOS transistor, a source region, a drain region and a channel region are formed in an SOI (Silicon On Insulator) layer. The definition of a channel region will be described later. A semiconductor layer (silicon layer) on a buried insulating layer extends to a thickness of 1000 xc3x85 from the surface of a semiconductor substrate (SOI substrate). A silicon oxide layer as a buried insulating layer is disposed beneath the SOI layer. The profile shown in FIG. 22 can be obtained by a single ion implantation of boron at an acceleration voltage of 20 keV and a dose of 4xc3x971012 cmxe2x88x922. A slight change in profile will be caused through a heat history. For example, curve L11 in FIG. 28 indicates the profile through a heat history of 15 minutes at 750xc2x0 C., 20 minutes at 800xc2x0 C., and 20 minutes at 850xc2x0 C., from the state indicated by curve L10 that illustrates the profile immediate after ion implantation. In general, annealing is performed at the stage of manufacturing of products, to suppress a change in profile after completion of the products.
Description will be now given of a channel region underlying the gate electrode as described in conventional MOS transistors. FIG. 23 shows a layout illustrating one construction of a conventional MOS transistor. In FIG. 23 a gate electrode 2 is formed on a semiconductor substrate 1. Within the semiconductor substrate 1, a source region 3 and a drain region 4 are disposed on each side of the gate electrode 2 as viewed from above the substrate 1. Specifically, the source region 3 and the drain region 4 are formed in a region except for the region beneath the gate electrode 2 in the semiconductor substrate 1. FIG. 24 is a cross-sectional view along the line Axe2x80x94A of FIG. 23. Under the gate electrode 2, there is formed a gate insulating film 8 on the surface of the semiconductor substrate 1. A silicon-on-insulator (SOI) layer 7 underlies the gate insulating film 8. The SOI layer 7 extends from above a silicon oxide film 5 to below the gate insulating film 8. Part of the SOI layer 7 which is disposed beneath the gate electrode 2 as viewed from above as in FIG. 23, namely, the region that underlies the gate insulating film 8, and is surrounded by the source region 3 and the drain region 4, is referred herein as channel region. That is, the SOI layer 7 that can be seen in the cross-section of FIG. 24 is a channel region. Other elements and the above MOS transistor that are formed in the semiconductor substrate 1 are isolated by a field oxide film 6. To isolate MOS transistors from each other which are formed by using an SOI layer, there can be employed a field shield isolation gate 100 as shown in FIG. 29. For instance, an N channel MOS transistor and a P channel MOS transistor which are formed by utilizing an SOI layer 7 are isolated from each other by a field shield isolation gate 100 provided between a gate 200 of the N channel MOS transistor and a gate 201 of the P channel MOS transistor. With respect to a P channel MOS transistor and an N channel MOS transistor in FIG. 29, a channel region is formed beneath a gate insulating film 8.
In the case where a channel region of an N channel MOS transistor has an impurity concentration profile as shown in FIG. 22, it has radiation resistance as shown in FIG. 25. Referring to the graph in FIG. 25, the characteristic indicated by the broken line L1 is obtained by measuring the MOS transistor under the conditions of a radiation dose of 140 Krad and a dose rate of 1.15xc3x97105 rad/hr. by using xcex3 rays from cobalt-60, and the characteristic indicted by the solid line L2 is obtained by measuring it in a room in the absence of radiation sources. At the time of measurement, the drain voltage of the MOS transistor is 2 V, and its source voltage, substrate voltage and body voltage are all 0 V. Here, the body voltage is the voltage of a channel region 7, and the substrate voltage is the voltage of an area underlying a silicon oxide film 5 of a semiconductor substrate 1. As can be seen from FIG. 25, the drain current is increased on the order of four figures by irradiating radiation when the gate voltage is 0 V.
This is because the threshold voltage of the N channel MOS transistor is reduced due to the irradiation of radiation. Upon irradiation of radiation, electron hole pairs are generated within the silicon oxide film 5. Electrons having a relatively high mobility will be cleaned out by electric field, whereas holes having a relatively low mobility will be captured by the silicon oxide film 5. The holes captured by the silicon oxide film 5 cause a decrease in the threshold voltage of the N channel MOS transistor, and thus leads to an increase in leakage voltage which involves an increase in electric power consumption.
Conventional semiconductor devices so constructed are unsuited for use in environmental conditions under which high radiation resistance is required.
According to a first aspect of the present invention, a semiconductor device comprises: an SOI substrate including a buried insulating layer and a semiconductor layer extending from above the buried insulating layer to one main surface; a gate insulating film disposed on the semiconductor layer; and a gate electrode disposed on the gate insulating film, wherein the semiconductor layer includes a channel region disposed in a region beneath the gate electrode, and source and drain regions disposed in a region except for the region beneath the gate electrode, so as to interpose the channel region therebetween; and the channel region has an impurity concentration profile peaking only at the boundary between the semiconductor layer and the buried insulating layer, or a position deeper than the boundary.
According to a second aspect of the present invention, in the semiconductor device, the semiconductor layer is not less than 1000 xc3x85 in thickness.
According to a third aspect of the present invention, the semiconductor device of the first aspect is an N channel MOS transistor.
According to a fourth aspect of the present invention, the semiconductor device of the first aspect is a P channel MOS transistor.
According to a fifth aspect of the present invention, a semiconductor device comprises: an SOI substrate including a buried insulating layer and a semiconductor layer extending from above the buried insulating layer to one main surface; a gate insulating film disposed on the semiconductor layer; and a gate electrode disposed on the gate insulating film, wherein the semiconductor layer includes a channel region of not less than 1000 xc3x85 in thickness, disposed in a region except for the region beneath the gate electrode, and source and drain regions disposed in a region except for the region beneath the gate electrode, so as to interpose the channel region therebetween; and the channel region has an impurity concentration profile peaking only in the vicinity of the boundary between the semiconductor layer and the buried insulating layer.
According to a sixth aspect of the present invention, the semiconductor device of the fifth aspect is an N channel MOS transistor.
The semiconductor device of the first or fifth aspect provides high radiation resistance or high punch through inhibition while suppressing an increase in threshold voltage.
The semiconductor device of the second aspect easily realizes the semiconductor device of the first aspect.
The semiconductor device of the third or sixth aspect reduces N channel MOS transistor errors due to radiation.
The semiconductor device of the fourth aspect reduces P channel MOS transistor malfunction due to punch through.
Accordingly, it is a principal object of the present invention to improve the radiation resistance of semiconductor devices.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.